Integrated circuit devices typically include a number of circuit sections interconnected with one another. While such integrated circuits can include sections custom designed at a device level, often circuit sections have a commonly understood functionality, such as a logic function and/or storage functions.
Designing integrated circuits can benefit from automation. For example, an integrated circuit can be initially represented at some higher level. Through automation and optimization, such a higher level design representation can be translated into more detailed forms, such as a netlist, a physical netlist, or a physical design.
Presently, most automated design approaches can be used to implement a design with a programmable logic device (PLD), or as an application specific integrated circuit (ASIC). In the case of a PLD, the more detailed design representation can be transformed into configuration data for the PLD, which can be used to program the PLD to the desired function. In the case of an ASIC, the more detailed design representation can be translated into a set of masks utilized to manufacture the integrated circuit. Currently, ASICs are typically composed of complementary metal-oxide-semiconductor (CMOS) type circuits.
Commonly owned, co-pending U.S. patent application Ser. Nos. 11/261,873 filed on Oct. 28, 2005, titled “INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS” published as U.S. Patent Publication US 2007/0096144 A1 on May 3, 2007, and 11/452,442 filed on Jun. 13, 1006, titled “CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES” published as U.S. Patent Publication US 2007/0262793 A1 on Nov. 15, 2007, both by Ashok K. Kapoor, disclose, amongst other matters, junction field effect transistors (JFETs) and related circuits formed by patterning a layer of polysilicon, or some other semiconductor material, deposited on a semiconductor substrate.
To better understand various features of the disclosed embodiments, a conventional integrated circuit section will now be described.
FIG. 24A shows a conventional CMOS-type six-transistor static random access memory (SRAM) cell 2400. FIG. 24B shows a schematic diagram representation of the SRAM cell of FIG. 24A. Transistors shown in FIG. 24B are identified by the same labels in FIG. 24A.
FIG. 24A shows shapes corresponding to five different layers 2402 to 2410, each shown with a different hatching pattern. Each layer can correspond to a different layer of an integrated circuit, or a different fabrication mask for the integrated circuit. Layer 2402 can be an n-channel MOS transistor active area. More particularly, layer 2402 can define a region of a semiconductor substrate initially doped to a p-type conductivity. Similarly, layer 2404 can be a p-channel MOS transistor active area. For example, layer 2404 can define a region of a substrate initially doped to an n-type conductivity.
Layer 2406 can be a polycrystalline silicon (polysilicon) layer that provides gates for MOS devices, as well as interconnections for such gates. Layer 2408 can be first metallization layer formed over polysilicon layer 2406 that can provide interconnections between transistor gates and sources/drains as well as complementary bit lines BL and /BL. Layer 2410 can be a second metallization layer formed over the first metallization layer 2408 that can form a word line WL, as well as supply lines for a high power supply VDD and a low power supply VG.
In the very particular example of FIG. 24A, it is assumed that a minimum feature size of a process utilized to manufacture the SRAM cell can be defined by the value 2λ. Further, a resulting SRAM cell can have dimensions 46λ×56λ.